FIG. 1 illustrates a schematic block diagram of a portion of a computer system. As shown, a central processing unit is coupled to cache memory and to a north bridge. The north bridge is coupled to memory, an accelerated graphics port (AGP) bus, and a peripheral component interconnect (PCI) bus. The central processing unit address memory in system virtual address space, or linear address space. To communicate with the north bridge, the central processing unit converts addresses in virtual address space to addresses in physical address space. To make such a conversion, the central processing unit often utilizes page address translation and includes a translation look-aside table (TLB) for storing the conversions.
The north bridge, upon receiving an address in physical address space from the central processing unit, determines whether the address corresponds to memory, PCI address space, or AGP memory space. If the address is directed towards the AGP address space, the north bridge makes a further translation of the received physical address utilizing a graphics address relocation table (GART) translation. The translated address is then stored in a GART TLB. As such, for the central processing unit to communicate with the AGP bus, two address space translations occur utilizing separate paging, page address translations and two separate TLBs are maintained.
FIG. 2 illustrates a graphical representation of address space within the system of FIG. 1. As shown, the system virtual address space, which corresponds to the central processing unit, has memory space for input/output transactions, kernels and processes. The system virtual addresses are converted to physical addresses as previously discussed. The physical address space includes PCI address space, AGP address space, main memory address space, and DOS address space. The main memory address space corresponds to the DRAM address space, while the PCI address space corresponds to the PCI address space along the PCI bus. As shown, for the AGP address space needs to be converted through a GART translation and is stored in main memory. Hence the need for the extra conversion.
FIG. 3 illustrates a logic diagram of a method for address translations. The process begins with the central processing unit determining whether an address has a corresponding translation in its TLB. If not, the CPU indexes, based on a portion of the linear address, a page directory to obtain a page directory entry (PDE). The central processing unit then indexes a page table based on the PDE and another portion of the linear address to obtain a page table entry (PTE). At this point, the central processing unit obtains the physical address based on the page table entry and yet another portion of the virtual, or linear, address. In a typical 32 bit virtual address, the first ten bits are used to address the page directory, the next ten bits are used to address the page table and the remaining bits correspond the least significant bits of the physical address. Note that if the translation has been stored in the TLB, the central processing unit may retrieve the physical address directly from the TLB.
Having obtained the physical address, the central processing unit determines whether the data is cached. If so, the process is done for this particular address. If not, the central processing unit passes the physical address to the north bridge. Upon receiving the physical address, the north bridge determines whether the physical address is in the AGP window. If not, the north bridge causes the corresponding data to be read from memory and sent to the central processing unit. If, however, the physical address is in the AGP window, the north bridge determines whether an AGP translated address is stored in a GART TLB. If so, the translated address is used to retrieve data from memory, which data is subsequently provided to the central processing unit. If, however, a GART TLB entry is not stored, the north bridge performs an AGP translation using a GART table.
As such when addresses produced by the central processing unit correspond to the AGP window, two translations occur. In existing computer systems, the two translations are done by the central processing unit and the north bridge. As such, each device contains a separate TLB. Such redundancy adds extra processing steps to address translations and produces overlapping data storage. In addition, it is more difficult to cache data from memory within the AGP window because the second address translation occurs within the north bridge.
Therefore, a need exists for a method and apparatus that more efficiently performs virtual address translations.